Vector multiplication with accumulation in large register space

ABSTRACT

An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.

The present patent application is a continuation application claimingpriority to U.S. patent application Ser. No. 13/538,523, filed Jun. 29,2012 and titled “Vector Multiplication With Accumulation In LargeRegister Space”, which is incorporated herein by reference in itsentirety.

BACKGROUND

Field of Invention

The present invention pertains to the computing sciences generally, and,more specifically to an apparatus and method for vector multiplicationwith accumulation in large register space.

Background

FIG. 1 shows a high level diagram of a processing core 100 implementedwith logic circuitry on a semiconductor chip. The processing coreincludes a pipeline 101. The pipeline consists of multiple stages eachdesigned to perform a specific step in the multi-step process needed tofully execute a program code instruction. These typically include atleast: 1) instruction fetch and decode; 2) data fetch; 3) execution; 4)write-back. The execution stage performs a specific operation identifiedby an instruction that was fetched and decoded in prior stage(s) (e.g.,in step 1) above) upon data identified by the same instruction andfetched in another prior stage (e.g., step 2) above). The data that isoperated upon is typically fetched from (general purpose) registerstorage space 102. New data that is created at the completion of theoperation is also typically “written back” to register storage space(e.g., at stage 4) above).

The logic circuitry associated with the execution stage is typicallycomposed of multiple “execution units” or “functional units” 103_1 to103_N that are each designed to perform its own unique subset ofoperations (e.g., a first functional unit performs integer mathoperations, a second functional unit performs floating pointinstructions, a third functional unit performs load/store operationsfrom/to cache/memory, etc.). The collection of all operations performedby all the functional units corresponds to the “instruction set”supported by the processing core 100.

Two types of processor architectures are widely recognized in the fieldof computer science: “scalar” and “vector”. A scalar processor isdesigned to execute instructions that perform operations on a single setof data, whereas, a vector processor is designed to execute instructionsthat perform operations on multiple sets of data. FIGS. 2A and 2Bpresent a comparative example that demonstrates the basic differencebetween a scalar processor and a vector processor.

FIG. 2A shows an example of a scalar AND instruction in which a singleoperand set, A and B, are ANDed together to produce a singular (or“scalar”) result C (i.e., AB=C). By contrast, FIG. 2B shows an exampleof a vector AND instruction in which two operand sets, A/B and D/E, arerespectively ANDed together in parallel to simultaneously produce avector result C, F (i.e., A.AND.B=C and D.AND.E=F). As a matter ofterminology, a “vector” is a data element having multiple “elements”.For example, a vector V=Q, R, S, T, U has five different elements: Q, R,S, T and U. The “size” of the exemplary vector V is five (because it hasfive elements).

FIG. 1 also shows the presence of vector register space 104 that isdifferent that general purpose register space 102. Specifically, generalpurpose register space 102 is nominally used to store scalar values. Assuch, when, the any of execution units perform scalar operations theynominally use operands called from (and write results back to) generalpurpose register storage space 102. By contrast, when any of theexecution units perform vector operations they nominally use operandscalled from (and write results back to) vector register space 107.Different regions of memory may likewise be allocated for the storage ofscalar values and vector values.

Note also the presence of masking logic 104_1 to 104_N and 105_1 to105_N at the respective inputs to and outputs from the functional units103_1 to 103_N. In various implementations, only one of these layers isactually implemented—although that is not a strict requirement. For anyinstruction that employs masking, input masking logic 104_1 to 104_Nand/or output masking logic 105_1 to 105_N may be used to control whichelements are effectively operated on for the vector instruction. Here, amask vector is read from a mask register space 106 (e.g., along withinput data vectors read from vector register storage space 107) and ispresented to at least one of the masking logic 104, 105 layers.

Over the course of executing vector program code each vector instructionneed not require a full data word. For example, the input vectors forsome instructions may only be 8 elements, the input vectors for otherinstructions may be 16 elements, the input vectors for otherinstructions may be 32 elements, etc. Masking layers 104/105 aretherefore used to identify a set of elements of a full vector data wordthat apply for a particular instruction so as to effect different vectorsizes across instructions. Typically, for each vector instruction, aspecific mask pattern kept in mask register space 106 is called out bythe instruction, fetched from mask register space and provided to eitheror both of the mask layers 104/105 to “enable” the correct set ofelements for the particular vector operation.

FIG. 3 shows a standard “schoolbook” multiplication process within abase 10 system. As observed in FIG. 3, each digit in a multiplicand 301is multiplied by each digit in a multiplier 302 to create an array ofpartial products 303. Each partial product is aligned with the locationof its respective multiplier digit. The aligned partial product termsare added together to produce multiplication result 304.

Note the presence of the carry terms 305. Carry terms 305_1 through305_5 can be created not only when the partial product terms are addedto produce the final result, but also, as part of the determination ofeach partial product term itself. For example, carry term 305_1 iscreated during the summation of the partial products, while, each ofcarry terms 305_2 through 305_4 is generated in determining a particularpartial product.

In order to perform multiplication operations a processing core embeddedon a semiconductor chip essentially performs mathematical operationsthat are similar to the multiplication processes discussed above.Specifically, partial product terms are generated, and, the partialproduct terms are added to produce a final result. In the case of vectorinstructions, however, carry terms can present problems.

For example, any “special logic circuitry” needed to recognize andaccount for any generated carry terms can become substantial in size assuch logic circuitry would be needed for every element of the maximumvector size supported by the processor. Non-vector “integer” executionlogic of a processor may be designed to use special “flags” andcorresponding flag circuitry to handle carry terms. However, as integeroperations are essentially scalar operations, only one instance of suchcircuitry needs to be implemented.

As such, a common processor design point for a processor that supportsboth integer and vector instructions is to design special flag circuitryfor the integer instructions but not the vector instructions (or atleast a limited version of flag circuitry for the vector instructions).Without the flag circuitry and its corresponding support for carryterms, the designers of a processor's vector instruction execution logicface the challenge of accounting for carry terms in their vectormultiplication instruction execution logic by some other technique.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings, in which likereferences indicate similar elements and in which:

FIG. 1 (Prior Art) shows an instruction processing pipeline;

FIGS. (Prior Art) 2 a and 2 b pertain to vector processing;

FIG. 3 (Prior Art) shows an example of school book multiplication;

FIG. 4a shows a process for accounting for carry terms by accumulatingsummed values in register space that is larger than multiplier andmultiplicand digit size;

FIG. 4b shows an example of the process of FIG. 4 a;

FIG. 4c shows an example of school book multiplication for comparisonagainst FIG. 4 b;

FIG. 4d shows a sequence of instructions that can perform the exemplarymethod of FIG. 4 b;

FIG. 4e shows an exemplary process for converting the base system of theresultant multiplication into the original base system of themultiplicand and multiplier;

FIG. 5a shows an embodiment of execution unit logic circuitry for aVMULTADDLO instruction;

FIG. 5b shows an embodiment of execution unit logic circuitry for aVMULTADDHI instruction;

FIG. 5c shows reuse of the design of an integer multiplier for theVMULTADDLO and VMULTADDHI instructions;

FIG. 6A illustrates an exemplary AVX instruction format;

FIG. 6B illustrates which fields from FIG. 6A make up a full opcodefield and a base operation field;

FIG. 6C illustrates which fields from FIG. 6A make up a register indexfield;

FIGS. 7A-7B are block diagrams illustrating a generic vector friendlyinstruction format and instruction templates thereof according toembodiments of the invention;

FIGS. 8A-8D are block diagrams illustrating an exemplary specific vectorfriendly instruction format according to embodiments of the invention;

FIG. 9 is a block diagram of a register architecture according to oneembodiment of the invention;

FIG. 10A is a block diagram illustrating both an exemplary in-orderpipeline and an exemplary register renaming, out-of-orderissue/execution pipeline according to embodiments of the invention;

FIG. 10B is a block diagram illustrating both an exemplary embodiment ofan in-order architecture core and an exemplary register renaming,out-of-order issue/execution architecture core to be included in aprocessor according to embodiments of the invention;

FIGS. 11A-B illustrate a block diagram of a more specific exemplaryin-order core architecture, which core would be one of several logicblocks (including other cores of the same type and/or different types)in a chip;

FIG. 12 is a block diagram of a processor that may have more than onecore, may have an integrated memory controller, and may have integratedgraphics according to embodiments of the invention;

FIG. 13 is a block diagram of a exemplary system in accordance with anembodiment of the present invention;

FIG. 14 is a block diagram of a first more specific exemplary system inaccordance with an embodiment of the present invention;

FIG. 15 is a block diagram of a second more specific exemplary system inaccordance with an embodiment of the present invention;

FIG. 16 is a block diagram of a SoC in accordance with an embodiment ofthe present invention;

FIG. 17 is a block diagram contrasting the use of a software instructionconverter to convert binary instructions in a source instruction set tobinary instructions in a target instruction set according to embodimentsof the invention.

DETAILED DESCRIPTION

The present description discloses a technique for performing vectormultiplication by accumulating summed partial product terms in registershaving a width larger than the digits expressed in the partial productterms. Because summations are written to larger registers, any summationresult that exceeds the digit size, which in traditional implementationsproduce a “carry term” that would need to be handled with special carrylogic, naturally expands into the additional register space. As such,special carry logic such as flag logic and flag handling logic normallyused for integer operations need not be implemented for vectormultiplication operations. The original multiplicand and multiplieroperands of the vector multiplication technique may be expressed in abase system having a digit size that can fully consume the registersize. As such, the multiplication operation may be preceded by aconversion process that converts the input operands from their originalhigher base system to a lower base system characterized by smallerdigits. The result of the multiplication may subsequently be convertedback to the original base system.

FIGS. 4a depicts a process for performing multiplication that accountsfor carry terms by forcing summations of partial product terms to beaccumulated in a register size that is larger than the maximum number ofdigits that can result in the summation sequence. Because the registersize is larger than the size of the summation result there is “room” tostore any carry over from the addition within the register.

Referring to FIG. 4a , a conversion process may be executed 401 prior tothe multiplication to effectively convert the multiplicand andmultiplier into a lower base system so as to create digits that aresmaller in size than the registers that will store the summationsdetermined from them.

Partial product terms are then determined, their respective digitsaligned and added into a resultant, where, the register size holdingeach digit in the resultant is larger than the maximum digit size thatis possible given the respective sizes of the multiplicand andmultiplier 402. As the size of the digits in the resultant may expandbeyond the size of the digits that emanated from the initial conversion401, the resultant at the conclusion of the summation of partialproducts may be effectively expressed in a different base system thanthe specific base system that the multiplier and multiplier wereconverted into by the conversion process 401.

More specifically, the resultant may be expressed with a base value thatis between the respective base values of the original and convertedforms of the multiplier and multiplicand. For example, if the multiplierand multiplicand are initially expressed as radix 64 (i.e., 2⁶⁴, or, 64bit digits) and the conversion process 401 converts the multiplier andmultiplicand into radix 52 (i.e., 2⁵², or, 52 bit digits), the resultantof multiplication 402 may be expressed radix m (i.e., 2^(m), or, m bitdigits) where 64>m>52.

As such, another conversion process 403 is performed to convert themultiplication resultant into the base system that the multiplicand andmultiplier were originally expressed in prior to the initial conversionprocess 401.

FIG. 4b shows an example of the process discussed just above withrespect to FIG. 4a . The specific example of FIG. 4b is furthersupported by FIGS. 4c and 4d which will be discussed in more detailbelow. The specific example of FIGS. 4b through 4d are directed to asystem where the multiplicand and multiplier are initially expressed inradix 64 form and are converted into radix 52 form in the initialconversion 401. It should be readily apparent to those of ordinary skillthat the teachings herein extend to any base system.

Referring to FIG. 4b , the multiplicand 404_1 and multiplier 405_1 mayeach be initially represented with a respective vector where eachelement of the vector corresponds to a different 64 bit digit of themultiplier or multiplicand.

A conversion process 406 may then convert, again as an example, themultiplier and multiplicand such that they are each represented with 52bit digits 404_2 and 405_2. In so doing, the number of digits (i.e., thevector size) of either or both of the multiplier and multiplicand mayincrease as part of the conversion process (even through the numericalvalue is unchanged on either side of the conversion process). Forexample, as observed in FIG. 4b , the initial multiplicand 404_1 isexpressed as a three element vector and the initial multiplier 405_1 isexpressed as a two element vector. The conversion process 406 isobserved to convert the multiplicand 404_1 into a four element vector404_2 and the multiplier 405_1 into a three element vector 405_2.

Here, note that each digit of the converted operands 404_2, 405_2depicts a left-wise field of 0s (e.g., left-wise field 407). Thisrepresentational feature is meant to depict the conversion from 64 bitdigits in the original operands 404_1, 405_1 to 52 bit digits in theconverted operands 404_2, 405_ 2. Notably, the physical hardware used tocontain the converted operands 404_2, 405_2 is still “wide enough” tohold 64 bit digits. As such, each converted 52 bit digit is left-wiseappended with a field of 12 zeros. Said another way, each element of theconverted vectors 404_2, 405_2 is a 64 bit element which contains a 52bit digit appended by 12 packed zeros on its left side.

The multiplicand and multiplier 404_2, 405_2 as represented in their new“52 bit digit format” are then multiplied 408. In the example of FIG. 4b, because the multiplication of two 52 bit digits can produce a 104 bitresult, and, only 64 bit vector element sizes are supported by theunderlying hardware, two different vector instruction types (VPMULADDLOand VPMULADDHI) are used to separately provide the “lower ordered” 52bits of the partial product terms and the “higher ordered” 52 bits ofthe partial product terms.

Here, referring to FIG. 4c , FIG. 4c shows standard schoolbook form ofthe partial products of the converted multiplicand 404_2 and multiplier405_2. Note that the partial product terms respect the fact that themultiplication of two 52 bit digits can result in a 104 bit digit. Assuch, for example, the partial product of the a′0 and b′0 digits 420consumes two vector element locations 420_1, 420_2, (a “HI” and a “LO”)each location supporting 52 bits with 12 left-wise packed zeros.

Accordingly, a first type of instruction (VPMULADDLO) is used todetermine the lower of the vector elements 420_1 of the partial productterm 420, and, a second type of instruction (VPMULADDHI) is used todetermine the higher of the vector elements 420_2 of the partialproducts. Essentially, VPMULADDLO returns the lower 52 bits of the 104bit resultant of a′0 X b′0, and, VPMULADDHI returns the higher 52 bitsof the 104 bit resultant of a′0 x b′0. Other embodiments may be designedwhere the upper and lower portions of the multiplication that arecalculated or accumulated by the instructions are something other thanan upper half and a lower half.

Returning to FIG. 4b , note that the individual digits of the partialproduct terms have been rearranged to take advantage of vector operationof the VPMULADD instructions and “pack” the operands so as to consumeless total instructions. Nevertheless, the summation through a specificdigit (vector element) location is correct when compared against theschoolbook format of FIG. 4c . For example, summation 421_1 of FIG. 4bsums the same partial product digits as summation 421_2 of FIG. 4 c.

In order to take advantage of the vector operation of the VPMULADDinstructions, note that a broadcast instruction may be executed prior toexecution of the VPMULADD instructions in order to create one of itsoperands. FIG. 4d shows an instruction level representation of theexemplary multiplication of FIG. 4b . Here, the conversion 406 of the 64bit digit multiplicand and multiplier operands 404_1, 405_1 into 52 bitdigit operands 404_2, 405_ 2 is performed with instruction(s) 430. Asthe mathematical execution for converting digits from one base system toanother is readily achievable to those of ordinary skill, an example ofthe specific instruction(s) need not be provided in the presentdiscussion.

After conversion, the newly formatted 52 bit digit operands 404_2, 405_2are stored in vector register R1 (which stores the multiplicand 501_2)and vector register R2 (which stores the multiplier 502_2). A vectorwhose size is at least equal to the maximum size of the multiplicationresult and whose elements are each zero is also created and stored inR3. Here, an iteration counter i is set to i=0 as an initial condition.A first broadcast instruction (VBROADCAST) is then executed 431 whichextracts the lowest ordered element of the multiplier in R2 (i.e., b′0)and replicates it across the vector size of the multiplicand 404_2. Inthis case, multiplicand 404_2 has four elements. As such, the firstVBROADCAST instruction 431 returns in R4 a vector having four copies ofb′0 as its four lowest ordered vector element locations.

A VPMULADDLO instruction 432 and a VPMULADDHI instruction 434 are eachexecuted subsequently where each instruction accepts the contents of R1,R3 and R4 as its input operands. In the particular embodiment of FIG. 4d, the VPMULADDLO and VPMULADDHI instructions are “multiply accumulate”instructions. As such, the instructions not only perform vectormultiplication, but also, vector addition. FIG. 5a shows an embodimentof the logic design of a VPMULADDLO execution unit and FIG. 5b shows anembodiment of the logic design of a VPMULADDHI execution unit.

Each execution unit includes an array of multipliers and adders, where,each individual multiplier and adder within the array is capable ofoperating from same positioned elements of two input vectors but eachmultiplier and adder operates from a different vector element position.For simplicity FIGS. 5a and 5b only show a multiplier 501 andcorresponding adder 502 of one vector element position.

As observed in FIG. 5a , the size of the register space used to holdeach input operand presented to the multiplier 501 is X bits (e.g., 64bits). However, a maximum of K (e.g., 52 bits) bits of these are used bythe multiplier in performing the multiplication where K<X. Notably theregister space used to hold each input operand can be used to holdelements of other vectors of vector operations other than the vectoroperations presently being described, where, the maximum width of theregister space X (e.g., 64 bits) can be utilized for input operand data.These other vector operations may be performed with execution logiccircuitry other than then execution logic circuitry of FIG. 5a and FIG.5b . The execution logic circuitry used to perform the other vectoroperations may be implemented within execution units of the pipelineother than the execution unit(s) that the execution logic circuitry ofFIG. 5a and FIG. 5b is implemented within. As such, the other executionlogic/execution unit support vector operations having input operandsexpressed in a base system that is higher than the base system of theinput operands utilized by the logic circuitry of FIGS. 5a and 5 b.

The maximum size of the substantive resultant of the multiplication isL=2 Kbits. The execution logic of the VPMULADDLO instruction, asobserved in FIG. 5a , for a particular vector element location, extractsa lower Q (e.g., 52) bits of the multiplication result and feeds thesebits into one input of an adder. A third input operand is respectivelyprovided to a second input of the adder. Here, the third input vectoroperand corresponds to a respective element of a third input vectoroperand.

In the particular embodiment of FIGS. 5a and 5b , the resultant of theaddition operation performed by the adder 502 is stored “back” in thesame register that provided the third (additive) input operand. As such,in this particular embodiment, the VPMULADDLO and VPMULADDHIinstructions have an instruction format that supports definition of bothan input operand “source” register and resultant “destination” registeras the same register.

The execution of the VPMULADDHI instruction is similar to that of theVPMULADDLO instruction except that the higher Q bits of themultiplication resultant are fed to the multiplier's respective adder.

Referring back to FIG. 4d , the initial execution of the VPMULADDLOinstruction 432 provides, in R3, the lower 52 bits of the multiplicationof b′0 with a′3 through a′0 as kept in R4.

As such, referring to FIG. 4b , the set of partial product terms 440 canbe viewed as any of: i) the output of the respective multipliers of theVPMULADDLO instruction 432; or, ii) the contents of R3 after theexecution of the initial VPMULADDLO instruction 432 is complete. Thecontents of R3 are formally represented in data structure 441 of FIG. 4b. As will be more clear in the following discussion, R3 behaves as anaccumulator that collects partial sums of the partial product terms overthe course of the multiplication sequence.

Referring to FIG. 4 d, the contents of R4 are then shifted 433 to theleft by one vector element location to setup correct alignment of theinput operands for the VPMULADDHI instruction. The VPMULADDHIinstruction is then executed 434. Data structure 442 of FIG. 4b showsthe results of the output of the multipliers during the course of theexecution of the initial VPMULADDHI instruction 434.

The addition operation of the VPMULADDHI instruction 434 adds thecontents of R3 (i.e., the resultant of the prior VPMULADDLO instruction432) and stores the result of the addition “back into” R3. As such,referring to data structure 441 of FIG. 4b , R3 now holds: i) partialproduct term 443 in the lowest ordered element 444; ii) the summation ofpartial product terms 445 and 446 in the second to lowest orderedelement 447; iii) the summation of partial product terms 448 and 449 inelement 450; iv) the summation of partial product terms 451 and 452 inelement 453.

The instruction pattern of instructions 431 through 434 of FIG. 4d isthen repeated for each NEXT i until the multiplication complete (afterthe i=3 iteration is complete). With each completion of each iteration(i.e., the completion of each VPMULADDHI instruction) summed alignedpartial products are accumulated in R3.

Notably, over the course of the summations and correspondingaccumulation within R3, the size of the digits in any of the elements ofR3 may have exceeded 52 bits.

As R3 is implemented in this example with hardware that supports vectorshaving element sizes of 64 bits, there is sufficient room in each of theelements of R3 to accommodate the expansion of the digit size.

Lastly, as the digit size of the accumulated values in R3 may haveexpanded at the completion of the multiplication to a value greater than52, the base system represented in R3 after multiplication is completemay no longer be radix 52. As such, a conversion 435 from the resultingbase system of R3 to the original radix 64 system is performed.

FIG. 4e shows an example of a process flow for converting the resultantof the multiplication into the original base system of the multiplicandand multiplier. According to the process of FIG. 4e , assume that theoriginal base system of the multiplicand and multiplier was a radix Msystem (i.e., 2M, or, M digits). In the example discussed above withrespect to FIGS. 4b and 4d , M=64. According to the process of FIG. 4e ,the maximum digit size of the digits in the multiplication result isidentified 460. In an embodiment, this is performed by identifying thebit location of the most significant “1” of all the digits in themultiplication result. As observed in FIG. 4, the maximum digit size iskept as a variable K. Thus, for example, if the most significant bitamongst the digits in the multiplication result of the example of FIGS.4b and 4d was located in the 55^(th) bit position, K=55.

A variable TEMP is set to a value 0 as an initial condition 461. Thevalue of TEMP is added 462 to the value of the next lowest ordered digitin the multiplication result (which, for the initial iterationcorresponds to the lowest ordered digit in the multiplication result).The value of TEMP is then divided by 2^(M) and the remainder is kept ina variable V 463. The value of V is retained/recognized as the nextleast ordered digit in the original (2^(M)) base system 464 (which,again, for the initial iteration corresponds to the lowest ordered digitin the multiplication result). The value of TEMP is then recalculated asTEMP/(2^(M)) 465 and the process iteratively repeats for each next digitin the multiplication result until each digit in the multiplicationresult has been processed.

Referring to FIGS. 5a and 5b , it is pertinent to point out that any ofthe depicted SourceDest, Source1 or Source 2 registers may be: i)registers in the vector register space of the processing core; ii)registers within an operand fetch stage of the instruction pipeline thatpreset operands to the execution unit; or, iii) registers at the “frontend” of the execution unit (e.g., that receive input operands from aninstruction fetch stage of the instruction execution pipeline).

FIG. 5c shows that the design of multiplier 501 of the execution unitsof FIGS. 5a and 5b may be substantially the same if not identical to thedesign of a multiplier within an integer(as opposed to vector) executionunit of an instruction execution pipeline 550 of a processing core.Here, as is known in the art, integer processing can be performed in afloating point format. According to one common approach, the mantissa ofthe floating point format is 53 bits. As such, in order to supportinteger floating point multiplication operations, there exists in theinstruction execution pipeline 550 an integer execution unit 551 that iscoupled to or otherwise receives operands from integer register space552 and contains a 53 bit by 53 bit multiplier 553.

In an embodiment, the same (or substantially the same) design for theinteger multiplier 553 is “ported over” and “reused” within theexecution unit(s) 554, 555 that support the improved vectormultiplication discussed at length above. As such, multiple instances ofthe same/substantially the same multiplier design is not onlyeffectively coupled to the integer register space 552 of the instructionexecution pipeline 550 but also the vector register space of the 556 ofthe instruction execution pipeline 550. In particular, note that thesize of the digits supported by the integer multiplier may be greaterthan or equal to the number of bits that corresponds to the lower basesystem that digits of the vector multiplication's multiplicand andmultiplier are converted down to from their original base systemexpression.

The enclosed techniques and methods are expected to be particularlyuseful when embedded in cryptographic processes including public keycryptographic processes such as RSA, DSA, GF(p), GF(p*q), GF(n)), ECCover GF(p) or DH key exchange processes.

The instruction format of the VPMULADDHI and VPMULADDLO instructions canbe implemented in various ways. Essentially, each of the VPMULADDHI andVPMULADDLO instructions can be viewed as vector instructions thatmultiply K bit elements but accumulate the resultant products of the Kbit elements in X bit elements, where X>K. In various embodiments X andK may be specified in the instruction format. For example, X and K (andwhether the HI or LO product portions is to be accumulated) may beeffectively specified in any opcode information of the instructionformat and/or, any immediate operand information of the instructionformat. The following discussion pertains to some specific vectorinstruction format embodiments. Here, X and K (and whether a HI or LOportion is accumulated) may be effectively encoded into any suitablefield of information discussed below including but not limited to anyopcode and/or immediate operand information.

FIG. 6A illustrates an exemplary AVX instruction format including a VEXprefix 602, real opcode field 630, Mod R/M byte 640, SIB byte 650,displacement field 662, and IMM8 672. FIG. 6B illustrates which fieldsfrom FIG. 6A make up a full opcode field 674 and a base operation field642. FIG. 6C illustrates which fields from FIG. 6A make up a registerindex field 644.

VEX Prefix (Bytes 0-2) 602 is encoded in a three-byte form. The firstbyte is the Format Field 640 (VEX Byte 0, bits [7:0]), which contains anexplicit C4 byte value (the unique value used for distinguishing the C4instruction format). The second-third bytes (VEX Bytes 1-2) include anumber of bit fields providing specific capability. Specifically, REXfield 605 (VEX Byte 1, bits [7-5]) consists of a VEX.R bit field (VEXByte 1, bit [7]-R), VEX.X bit field (VEX byte 1, bit [6]-X), and VEX.Bbit field (VEX byte 1, bit[5]-B). Other fields of the instructionsencode the lower three bits of the register indexes as is known in theart (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed byadding VEX.R, VEX.X, and VEX.B. Opcode map field 615 (VEX byte 1, bits[4:0]-mmmmm) includes content to encode an implied leading opcode byte.W Field 664 (VEX byte 2, bit [7]-W)—is represented by the notationVEX.W, and provides different functions depending on the instruction.The role of VEX.vvvv 620 (VEX Byte 2, bits [6:3]-vvvv) may include thefollowing: 1) VEX.vvvv encodes the first source register operand,specified in inverted (1s complement) form and is valid for instructionswith 2 or more source operands; 2) VEX.vvvv encodes the destinationregister operand, specified in is complement form for certain vectorshifts; or 3) VEX.vvvv does not encode any operand, the field isreserved and should contain 1111b. If VEX.L 668 Size field (VEX byte 2,bit [2]-L)=0, it indicates 128 bit vector; if VEX.L=1, it indicates 256bit vector. Prefix encoding field 625 (VEX byte 2, bits [1:0]-pp)provides additional bits for the base operation field.

Real Opcode Field 630 (Byte 3) is also known as the opcode byte. Part ofthe opcode is specified in this field.

MOD R/M Field 640 (Byte 4) includes MOD field 642 (bits [7-6]), Regfield 644 (bits [5-3]), and R/M field 646 (bits [2-0]). The role of Regfield 644 may include the following: encoding either the destinationregister operand or a source register operand (the rrr of Rrrr), or betreated as an opcode extension and not used to encode any instructionoperand. The role of R/M field 646 may include the following: encodingthe instruction operand that references a memory address, or encodingeither the destination register operand or a source register operand.

Scale, Index, Base (SIB)—The content of Scale field 650 (Byte 5)includes SS652 (bits [7-6]), which is used for memory addressgeneration. The contents of SIB.xxx 654 (bits [5-3]) and SIB.bbb 656(bits [2-0]) have been previously referred to with regard to theregister indexes Xxxx and Bbbb.

The Displacement Field 662 and the immediate field (IMM8) 672 containaddress data.

Generic Vector Friendly Instruction Format

A vector friendly instruction format is an instruction format that issuited for vector instructions (e.g., there are certain fields specificto vector operations). While embodiments are described in which bothvector and scalar operations are supported through the vector friendlyinstruction format, alternative embodiments use only vector operationsthe vector friendly instruction format.

FIGS. 7A-7B are block diagrams illustrating a generic vector friendlyinstruction format and instruction templates thereof according toembodiments of the invention. FIG. 7A is a block diagram illustrating ageneric vector friendly instruction format and class A instructiontemplates thereof according to embodiments of the invention; while FIG.7B is a block diagram illustrating the generic vector friendlyinstruction format and class B instruction templates thereof accordingto embodiments of the invention. Specifically, a generic vector friendlyinstruction format 700 for which are defined class A and class Binstruction templates, both of which include no memory access 705instruction templates and memory access 720 instruction templates. Theterm generic in the context of the vector friendly instruction formatrefers to the instruction format not being tied to any specificinstruction set.

While embodiments of the invention will be described in which the vectorfriendly instruction format supports the following: a 64 byte vectoroperand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) dataelement widths (or sizes) (and thus, a 64 byte vector consists of either16 doubleword-size elements or alternatively, 8 quadword-size elements);a 64 byte vector operand length (or size) with 16 bit (2 byte) or 8 bit(1 byte) data element widths (or sizes); a 32 byte vector operand length(or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8bit (1 byte) data element widths (or sizes); and a 16 byte vectoroperand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit(2 byte), or 8 bit (1 byte) data element widths (or sizes); alternativeembodiments may support more, less and/or different vector operand sizes(e.g., 256 byte vector operands) with more, less, or different dataelement widths (e.g., 128 bit (16 byte) data element widths).

The class A instruction templates in FIG. 7A include: 1) within the nomemory access 705 instruction templates there is shown a no memoryaccess, full round control type operation 710 instruction template and ano memory access, data transform type operation 715 instructiontemplate; and 2) within the memory access 720 instruction templatesthere is shown a memory access, temporal 725 instruction template and amemory access, non-temporal 730 instruction template. The class Binstruction templates in FIG. 7B include: 1) within the no memory access705 instruction templates there is shown a no memory access, write maskcontrol, partial round control type operation 712 instruction templateand a no memory access, write mask control, vsize type operation 717instruction template; and 2) within the memory access 720 instructiontemplates there is shown a memory access, write mask control 727instruction template.

The generic vector friendly instruction format 700 includes thefollowing fields listed below in the order illustrated in FIGS. 7A-7B.In conjunction with the discussions above of FIGS. 4 a,b,c,d and 5,a,b,cin an embodiment, referring to the format details provided below inFIGS. 7A-B and 8, either a non memory access instruction type 705 or amemory access instruction type 720 may be utilized. Addresses for theread mask(s), input vector operand(s) and destination may be identifiedin register address field 744 described below. In a further embodiment,the write mask is specified in write mask field 770.

Format field 740—a specific value (an instruction format identifiervalue) in this field uniquely identifies the vector friendly instructionformat, and thus occurrences of instructions in the vector friendlyinstruction format in instruction streams. As such, this field isoptional in the sense that it is not needed for an instruction set thathas only the generic vector friendly instruction format.

Base operation field 742—its content distinguishes different baseoperations.

Register index field 744—its content, directly or through addressgeneration, specifies the locations of the source and destinationoperands, be they in registers or in memory. These include a sufficientnumber of bits to select N registers from a P×Q (e.g. 32×512, 16×128,32×1024, 64×1024) register file. While in one embodiment N may be up tothree sources and one destination register, alternative embodiments maysupport more or less sources and destination registers (e.g., maysupport up to two sources where one of these sources also acts as thedestination, may support up to three sources where one of these sourcesalso acts as the destination, may support up to two sources and onedestination).

Modifier field 746—its content distinguishes occurrences of instructionsin the generic vector instruction format that specify memory access fromthose that do not; that is, between no memory access 705 instructiontemplates and memory access 720 instruction templates. Memory accessoperations read and/or write to the memory hierarchy (in some casesspecifying the source and/or destination addresses using values inregisters), while non-memory access operations do not (e.g., the sourceand destinations are registers). While in one embodiment this field alsoselects between three different ways to perform memory addresscalculations, alternative embodiments may support more, less, ordifferent ways to perform memory address calculations.

Augmentation operation field 750—its content distinguishes which one ofa variety of different operations to be performed in addition to thebase operation. This field is context specific. In one embodiment of theinvention, this field is divided into a class field 768, an alpha field752, and a beta field 754. The augmentation operation field 750 allowscommon groups of operations to be performed in a single instructionrather than 2, 3, or 4 instructions.

Scale field 760—its content allows for the scaling of the index field'scontent for memory address generation (e.g., for address generation thatuses 2^(scale)*index+base).

Displacement Field 762A—its content is used as part of memory addressgeneration (e.g., for address generation that uses2^(scale)*index+base+displacement).

Displacement Factor Field 762B (note that the juxtaposition ofdisplacement field 762A directly over displacement factor field 762Bindicates one or the other is used)—its content is used as part ofaddress generation; it specifies a displacement factor that is to bescaled by the size of a memory access (N)—where N is the number of bytesin the memory access (e.g., for address generation that uses2^(scale)*index+base+scaled displacement). Redundant low-order bits areignored and hence, the displacement factor field's content is multipliedby the memory operands total size (N) in order to generate the finaldisplacement to be used in calculating an effective address. The valueof N is determined by the processor hardware at runtime based on thefull opcode field 774 (described later herein) and the data manipulationfield 754C. The displacement field 762A and the displacement factorfield 762B are optional in the sense that they are not used for the nomemory access 705 instruction templates and/or different embodiments mayimplement only one or none of the two.

Data element width field 764—its content distinguishes which one of anumber of data element widths is to be used (in some embodiments for allinstructions; in other embodiments for only some of the instructions).This field is optional in the sense that it is not needed if only onedata element width is supported and/or data element widths are supportedusing some aspect of the opcodes.

Write mask field 770—its content controls, on a per data elementposition basis, whether that data element position in the destinationvector operand reflects the result of the base operation andaugmentation operation. Class A instruction templates supportmerging-writemasking, while class B instruction templates support bothmerging- and zeroing-writemasking. When merging, vector masks allow anyset of elements in the destination to be protected from updates duringthe execution of any operation (specified by the base operation and theaugmentation operation); in other one embodiment, preserving the oldvalue of each element of the destination where the corresponding maskbit has a 0. In contrast, when zeroing vector masks allow any set ofelements in the destination to be zeroed during the execution of anyoperation (specified by the base operation and the augmentationoperation); in one embodiment, an element of the destination is set to 0when the corresponding mask bit has a 0 value. A subset of thisfunctionality is the ability to control the vector length of theoperation being performed (that is, the span of elements being modified,from the first to the last one); however, it is not necessary that theelements that are modified be consecutive. Thus, the write mask field770 allows for partial vector operations, including loads, stores,arithmetic, logical, etc. While embodiments of the invention aredescribed in which the write mask field's 770 content selects one of anumber of write mask registers that contains the write mask to be used(and thus the write mask field's 770 content indirectly identifies thatmasking to be performed), alternative embodiments instead or additionalallow the mask write field's 770 content to directly specify the maskingto be performed.

Immediate field 772—its content allows for the specification of animmediate. This field is optional in the sense that is it not present inan implementation of the generic vector friendly format that does notsupport immediate and it is not present in instructions that do not usean immediate.

Class field 768—its content distinguishes between different classes ofinstructions. With reference to FIGS. 7A-B, the contents of this fieldselect between class A and class B instructions. In FIGS. 7A-B, roundedcorner squares are used to indicate a specific value is present in afield (e.g., class A 768A and class B 768B for the class field 768respectively in FIGS. 7A-B).

Instruction Templates of Class A

In the case of the non-memory access 705 instruction templates of classA, the alpha field 752 is interpreted as an RS field 752A, whose contentdistinguishes which one of the different augmentation operation typesare to be performed (e.g., round 752A.1 and data transform 752A.2 arerespectively specified for the no memory access, round type operation710 and the no memory access, data transform type operation 715instruction templates), while the beta field 754 distinguishes which ofthe operations of the specified type is to be performed. In the nomemory access 705 instruction templates, the scale field 760, thedisplacement field 762A, and the displacement scale filed 762B are notpresent.

No-Memory Access Instruction Templates—Full Round Control Type Operation

In the no memory access full round control type operation 710instruction template, the beta field 754 is interpreted as a roundcontrol field 754A, whose content(s) provide static rounding. While inthe described embodiments of the invention the round control field 754Aincludes a suppress all floating point exceptions (SAE) field 756 and around operation control field 758, alternative embodiments may supportmay encode both these concepts into the same field or only have one orthe other of these concepts/fields (e.g., may have only the roundoperation control field 758).

SAE field 756—its content distinguishes whether or not to disable theexception event reporting; when the SAE field's 756 content indicatessuppression is enabled, a given instruction does not report any kind offloating-point exception flag and does not raise any floating pointexception handler.

Round operation control field 758—its content distinguishes which one ofa group of rounding operations to perform (e.g., Round-up, Round-down,Round-towards-zero and Round-to-nearest). Thus, the round operationcontrol field 758 allows for the changing of the rounding mode on a perinstruction basis. In one embodiment of the invention where a processorincludes a control register for specifying rounding modes, the roundoperation control field's 750 content overrides that register value.

No Memory Access Instruction Templates—Data Transform Type Operation

In the no memory access data transform type operation 715 instructiontemplate, the beta field 754 is interpreted as a data transform field754B, whose content distinguishes which one of a number of datatransforms is to be performed (e.g., no data transform, swizzle,broadcast).

In the case of a memory access 720 instruction template of class A, thealpha field 752 is interpreted as an eviction hint field 752B, whosecontent distinguishes which one of the eviction hints is to be used (inFIG. 7A, temporal 752B.1 and non-temporal 752B.2 are respectivelyspecified for the memory access, temporal 725 instruction template andthe memory access, non-temporal 730 instruction template), while thebeta field 754 is interpreted as a data manipulation field 754C, whosecontent distinguishes which one of a number of data manipulationoperations (also known as primitives) is to be performed (e.g., nomanipulation; broadcast; up conversion of a source; and down conversionof a destination). The memory access 720 instruction templates includethe scale field 760, and optionally the displacement field 762A or thedisplacement scale field 762B.

Vector memory instructions perform vector loads from and vector storesto memory, with conversion support. As with regular vector instructions,vector memory instructions transfer data from/to memory in a dataelement-wise fashion, with the elements that are actually transferred isdictated by the contents of the vector mask that is selected as thewrite mask.

Memory Access Instruction Templates—Temporal

Temporal data is data likely to be reused soon enough to benefit fromcaching. This is, however, a hint, and different processors mayimplement it in different ways, including ignoring the hint entirely.

Memory Access Instruction Templates—Non-Temporal

Non-temporal data is data unlikely to be reused soon enough to benefitfrom caching in the 1st-level cache and should be given priority foreviction. This is, however, a hint, and different processors mayimplement it in different ways, including ignoring the hint entirely.

Instruction Templates of Class B

In the case of the instruction templates of class B, the alpha field 752is interpreted as a write mask control (Z) field 752C, whose contentdistinguishes whether the write masking controlled by the write maskfield 770 should be a merging or a zeroing.

In the case of the non-memory access 705 instruction templates of classB, part of the beta field 754 is interpreted as an RL field 757A, whosecontent distinguishes which one of the different augmentation operationtypes are to be performed (e.g., round 757A.1 and vector length (VSIZE)757A.2 are respectively specified for the no memory access, write maskcontrol, partial round control type operation 712 instruction templateand the no memory access, write mask control, VSIZE type operation 717instruction template), while the rest of the beta field 754distinguishes which of the operations of the specified type is to beperformed. In the no memory access 705 instruction templates, the scalefield 760, the displacement field 762A, and the displacement scale filed762B are not present.

In the no memory access, write mask control, partial round control typeoperation 710 instruction template, the rest of the beta field 754 isinterpreted as a round operation field 759A and exception eventreporting is disabled (a given instruction does not report any kind offloating-point exception flag and does not raise any floating pointexception handler).

Round operation control field 759A—just as round operation control field758, its content distinguishes which one of a group of roundingoperations to perform (e.g., Round-up, Round-down, Round-towards-zeroand Round-to-nearest). Thus, the round operation control field 759Aallows for the changing of the rounding mode on a per instruction basis.In one embodiment of the invention where a processor includes a controlregister for specifying rounding modes, the round operation controlfield's 750 content overrides that register value.

In the no memory access, write mask control, VSIZE type operation 717instruction template, the rest of the beta field 754 is interpreted as avector length field 759B, whose content distinguishes which one of anumber of data vector lengths is to be performed on (e.g., 128, 256, or512 byte).

In the case of a memory access 720 instruction template of class B, partof the beta field 754 is interpreted as a broadcast field 757B, whosecontent distinguishes whether or not the broadcast type datamanipulation operation is to be performed, while the rest of the betafield 754 is interpreted the vector length field 759B. The memory access720 instruction templates include the scale field 760, and optionallythe displacement field 762A or the displacement scale field 762B.

With regard to the generic vector friendly instruction format 700, afull opcode field 774 is shown including the format field 740, the baseoperation field 742, and the data element width field 764. While oneembodiment is shown where the full opcode field 774 includes all ofthese fields, the full opcode field 774 includes less than all of thesefields in embodiments that do not support all of them. The full opcodefield 774 provides the operation code (opcode).

The augmentation operation field 750, the data element width field 764,and the write mask field 770 allow these features to be specified on aper instruction basis in the generic vector friendly instruction format.

The combination of write mask field and data element width field createtyped instructions in that they allow the mask to be applied based ondifferent data element widths.

The various instruction templates found within class A and class B arebeneficial in different situations. In some embodiments of theinvention, different processors or different cores within a processormay support only class A, only class B, or both classes. For instance, ahigh performance general purpose out-of-order core intended forgeneral-purpose computing may support only class B, a core intendedprimarily for graphics and/or scientific (throughput) computing maysupport only class A, and a core intended for both may support both (ofcourse, a core that has some mix of templates and instructions from bothclasses but not all templates and instructions from both classes iswithin the purview of the invention). Also, a single processor mayinclude multiple cores, all of which support the same class or in whichdifferent cores support different class. For instance, in a processorwith separate graphics and general purpose cores, one of the graphicscores intended primarily for graphics and/or scientific computing maysupport only class A, while one or more of the general purpose cores maybe high performance general purpose cores with out of order executionand register renaming intended for general-purpose computing thatsupport only class B. Another processor that does not have a separategraphics core, may include one more general purpose in-order orout-of-order cores that support both class A and class B. Of course,features from one class may also be implement in the other class indifferent embodiments of the invention. Programs written in a high levellanguage would be put (e.g., just in time compiled or staticallycompiled) into an variety of different executable forms, including: 1) aform having only instructions of the class(es) supported by the targetprocessor for execution; or 2) a form having alternative routineswritten using different combinations of the instructions of all classesand having control flow code that selects the routines to execute basedon the instructions supported by the processor which is currentlyexecuting the code.

Exemplary Specific Vector Friendly Instruction Format

FIGS. 8A-8D are block diagrams illustrating an exemplary specific vectorfriendly instruction format according to embodiments of the invention.FIGS. 8A-8D show a specific vector friendly instruction format 800 thatis specific in the sense that it specifies the location, size,interpretation, and order of the fields, as well as values for some ofthose fields. The specific vector friendly instruction format 800 may beused to extend the x86 instruction set, and thus some of the fields aresimilar or the same as those used in the existing x86 instruction setand extension thereof (e.g., AVX). This format remains consistent withthe prefix encoding field, real opcode byte field, MOD RIM field, SIBfield, displacement field, and immediate fields of the existing x86instruction set with extensions. The fields from FIG. 7 into which thefields from FIGS. 8A-8D map are illustrated.

It should be understood that, although embodiments of the invention aredescribed with reference to the specific vector friendly instructionformat 800 in the context of the generic vector friendly instructionformat 700 for illustrative purposes, the invention is not limited tothe specific vector friendly instruction format 800 except whereclaimed. For example, the generic vector friendly instruction format 700contemplates a variety of possible sizes for the various fields, whilethe specific vector friendly instruction format 800 is shown as havingfields of specific sizes. By way of specific example, while the dataelement width field 764 is illustrated as a one bit field in thespecific vector friendly instruction format 800, the invention is not solimited (that is, the generic vector friendly instruction format 700contemplates other sizes of the data element width field 764).

The generic vector friendly instruction format 700 includes thefollowing fields listed below in the order illustrated in FIG. 8A.

EVEX Prefix (Bytes 0-3) 802—is encoded in a four-byte form.

Format Field 740 (EVEX Byte 0, bits [7:0])—the first byte (EVEX Byte 0)is the format field 740 and it contains 0×62 (the unique value used fordistinguishing the vector friendly instruction format in one embodimentof the invention).

The second-fourth bytes (EVEX Bytes 1-3) include a number of bit fieldsproviding specific capability.

REX field 805 (EVEX Byte 1, bits [7-5])—consists of a EVEX.R bit field(EVEX Byte 1, bit [7]-R), EVEX.X bit field (EVEX byte 1, bit [6]-X), and757BEX byte 1, bit[5]-B). The EVEX.R, EVEX.X, and EVEX.B bit fieldsprovide the same functionality as the corresponding VEX bit fields, andare encoded using ls complement form, i.e. ZMM0 is encoded as 1111B,ZMM15 is encoded as 0000B. Other fields of the instructions encode thelower three bits of the register indexes as is known in the art (rrr,xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed by addingEVEX.R, EVEX.X, and EVEX.B.

REX′ field 710—this is the first part of the REX′ field 710 and is theEVEX.R′ bit field (EVEX Byte 1, bit [4]-R′) that is used to encodeeither the upper 16 or lower 16 of the extended 32 register set. In oneembodiment of the invention, this bit, along with others as indicatedbelow, is stored in bit inverted format to distinguish (in thewell-known x86 32-bit mode) from the BOUND instruction, whose realopcode byte is 62, but does not accept in the MOD R/M field (describedbelow) the value of 11 in the MOD field; alternative embodiments of theinvention do not store this and the other indicated bits below in theinverted format. A value of 1 is used to encode the lower 16 registers.In other words, R′Rrrr is formed by combining EVEX.R′, EVEX.R, and theother RRR from other fields.

Opcode map field 815 (EVEX byte 1, bits [3:0]-mmmm)—its content encodesan implied leading opcode byte (0F, 0F 38, or 0F 3).

Data element width field 764 (EVEX byte 2, bit [7]-W)—is represented bythe notation EVEX.W. EVEX.W is used to define the granularity (size) ofthe datatype (either 32-bit data elements or 64-bit data elements).

EVEX.vvvv 820 (EVEX Byte 2, bits [6:3]-vvvv)—the role of EVEX.vvvv mayinclude the following: 1) EVEX.vvvv encodes the first source registeroperand, specified in inverted (1s complement) form and is valid forinstructions with 2 or more source operands; 2) EVEX.vvvv encodes thedestination register operand, specified in is complement form forcertain vector shifts; or 3) EVEX.vvvv does not encode any operand, thefield is reserved and should contain 1111b. Thus, EVEX.vvvv field 820encodes the 4 low-order bits of the first source register specifierstored in inverted (ls complement) form. Depending on the instruction,an extra different EVEX bit field is used to extend the specifier sizeto 32 registers.

EVEX.U 768 Class field (EVEX byte 2, bit [2]-U)—If EVEX.U=0, itindicates class A or EVEX.U0; if EVEX.U=1, it indicates class B orEVEX.U1.

Prefix encoding field 825 (EVEX byte 2, bits [1:0]-pp)—providesadditional bits for the base operation field. In addition to providingsupport for the legacy SSE instructions in the EVEX prefix format, thisalso has the benefit of compacting the SIMD prefix (rather thanrequiring a byte to express the SIMD prefix, the EVEX prefix requiresonly 2 bits). In one embodiment, to support legacy SSE instructions thatuse a SIMD prefix (66H, F2H, F3H) in both the legacy format and in theEVEX prefix format, these legacy SIMD prefixes are encoded into the SIMDprefix encoding field; and at runtime are expanded into the legacy SIMDprefix prior to being provided to the decoder's PLA (so the PLA canexecute both the legacy and EVEX format of these legacy instructionswithout modification). Although newer instructions could use the EVEXprefix encoding field's content directly as an opcode extension, certainembodiments expand in a similar fashion for consistency but allow fordifferent meanings to be specified by these legacy SIMD prefixes. Analternative embodiment may redesign the PLA to support the 2 bit SIMDprefix encodings, and thus not require the expansion.

Alpha field 752 (EVEX byte 3, bit [7]-EH; also known as EVEX.EH,EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also illustratedwith α)—as previously described, this field is context specific.

Beta field 754 (EVEX byte 3, bits [6:4]-SSS, also known as EVEX.s₂₋₀,EVEX.r₂₋₀, EVEX.rr1, EVEX.LL0, EVEX.LLB; also illustrated with βββ)—aspreviously described, this field is context specific.

REX′ field 710—this is the remainder of the REX′ field and is theEVEX.V′ bit field (EVEX Byte 3, bit [3]-V′) that may be used to encodeeither the upper 16 or lower 16 of the extended 32 register set. Thisbit is stored in bit inverted format. A value of 1 is used to encode thelower 16 registers. In other words, V′VVVV is formed by combiningEVEX.V′, EVEX.vvvv.

Write mask field 770 (EVEX byte 3, bits [2:0]-kkk)—its content specifiesthe index of a register in the write mask registers as previouslydescribed. In one embodiment of the invention, the specific value EVEXkkk=000 has a special behavior implying no write mask is used for theparticular instruction (this may be implemented in a variety of waysincluding the use of a write mask hardwired to all ones or hardware thatbypasses the masking hardware).

Real Opcode Field 830 (Byte 4) is also known as the opcode byte. Part ofthe opcode is specified in this field.

MOD R/M Field 840 (Byte 5) includes MOD field 842, Reg field 844, andR/M field 846. As previously described, the MOD field's 842 contentdistinguishes between memory access and non-memory access operations.The role of Reg field 844 can be summarized to two situations: encodingeither the destination register operand or a source register operand, orbe treated as an opcode extension and not used to encode any instructionoperand. The role of R/M field 846 may include the following: encodingthe instruction operand that references a memory address, or encodingeither the destination register operand or a source register operand.

Scale, Index, Base (SIB) Byte (Byte 6)—As previously described, thescale field's 750 content is used for memory address generation. SIB.xxx854 and SIB.bbb 856—the contents of these fields have been previouslyreferred to with regard to the register indexes Xxxx and Bbbb.

Displacement field 762A (Bytes 7-10)—when MOD field 842 contains 10,bytes 7-10 are the displacement field 762A, and it works the same as thelegacy 32-bit displacement (disp32) and works at byte granularity.

Displacement factor field 762B (Byte 7)—when MOD field 842 contains 01,byte 7 is the displacement factor field 762B. The location of this fieldis that same as that of the legacy x86 instruction set 8-bitdisplacement (disp8), which works at byte granularity. Since disp8 issign extended, it can only address between −128 and 127 bytes offsets;in terms of 64 byte cache lines, disp8 uses 8 bits that can be set toonly four really useful values −128, −64, 0, and 64; since a greaterrange is often needed, disp32 is used; however, disp32 requires 4 bytes.In contrast to disp8 and disp32, the displacement factor field 762B is areinterpretation of disp8; when using displacement factor field 762B,the actual displacement is determined by the content of the displacementfactor field multiplied by the size of the memory operand access (N).This type of displacement is referred to as disp8*N. This reduces theaverage instruction length (a single byte of used for the displacementbut with a much greater range). Such compressed displacement is based onthe assumption that the effective displacement is multiple of thegranularity of the memory access, and hence, the redundant low-orderbits of the address offset do not need to be encoded. In other words,the displacement factor field 762B substitutes the legacy x86instruction set 8-bit displacement. Thus, the displacement factor field762B is encoded the same way as an x86 instruction set 8-bitdisplacement (so no changes in the ModRM/SIB encoding rules) with theonly exception that disp8 is overloaded to disp8*N. In other words,there are no changes in the encoding rules or encoding lengths but onlyin the interpretation of the displacement value by hardware (which needsto scale the displacement by the size of the memory operand to obtain abyte-wise address offset).

Immediate field 772 operates as previously described.

Full Opcode Field

FIG. 8B is a block diagram illustrating the fields of the specificvector friendly instruction format 800 that make up the full opcodefield 774 according to one embodiment of the invention. Specifically,the full opcode field 774 includes the format field 740, the baseoperation field 742, and the data element width (W) field 764. The baseoperation field 742 includes the prefix encoding field 825, the opcodemap field 815, and the real opcode field 830.

Register Index Field

FIG. 8C is a block diagram illustrating the fields of the specificvector friendly instruction format 800 that make up the register indexfield 744 according to one embodiment of the invention. Specifically,the register index field 744 includes the REX field 805, the REX′ field810, the MODR/M.reg field 844, the MODR/M.r/m field 846, the VVVV field820, xxx field 854, and the bbb field 856.

Augmentation Operation Field

FIG. 8D is a block diagram illustrating the fields of the specificvector friendly instruction format 800 that make up the augmentationoperation field 750 according to one embodiment of the invention. Whenthe class (U) field 768 contains 0, it signifies EVEX.U0 (class A 768A);when it contains 1, it signifies EVEX.U1 (class B 768B). When U=0 andthe MOD field 842 contains 11 (signifying a no memory access operation),the alpha field 752 (EVEX byte 3, bit [7]-EH) is interpreted as the rsfield 752A. When the rs field 752A contains a 1 (round 752A.1), the betafield 754 (EVEX byte 3, bits [6:4]-SSS) is interpreted as the roundcontrol field 754A. The round control field 754A includes a one bit SAEfield 756 and a two bit round operation field 758. When the rs field752A contains a 0 (data transform 752A.2), the beta field 754 (EVEX byte3, bits [6:4]-SSS) is interpreted as a three bit data transform field754B. When U=0 and the MOD field 842 contains 00, 01, or 10 (signifyinga memory access operation), the alpha field 752 (EVEX byte 3, bit[7]-EH) is interpreted as the eviction hint (EH) field 752B and the betafield 754 (EVEX byte 3, bits [6:4]-SSS) is interpreted as a three bitdata manipulation field 754C.

When U=1, the alpha field 752 (EVEX byte 3, bit [7]-EH) is interpretedas the write mask control (Z) field 752C. When U=1 and the MOD field 842contains 11 (signifying a no memory access operation), part of the betafield 754 (EVEX byte 3, bit [4]-S₀) is interpreted as the RL field 757A;when it contains a 1 (round 757A.1) the rest of the beta field 754 (EVEXbyte 3, bit [6-5]-S₂₋₁) is interpreted as the round operation field759A, while when the RL field 757A contains a 0 (VSIZE 757.A2) the restof the beta field 754 (EVEX byte 3, bit [6-5]-S₂₋₁) is interpreted asthe vector length field 759B (EVEX byte 3, bit [6-5]-L₁₋₀). When U=1 andthe MOD field 842 contains 00, 01, or 10 (signifying a memory accessoperation), the beta field 754 (EVEX byte 3, bits [6:4]-SSS) isinterpreted as the vector length field 759B (EVEX byte 3, bit[6-5]-L₁₋₀) and the broadcast field 757B (EVEX byte 3, bit [4]-B).

Exemplary Register Architecture

FIG. 9 is a block diagram of a register architecture 900 according toone embodiment of the invention. In the embodiment illustrated, thereare 32 vector registers 910 that are 512 bits wide; these registers arereferenced as zmm0 through zmm31. The lower order 256 bits of the lower16 zmm registers are overlaid on registers ymm0-16. The lower order 128bits of the lower 16 zmm registers (the lower order 128 bits of the ymmregisters) are overlaid on registers xmm0-15. The specific vectorfriendly instruction format 800 operates on these overlaid register fileas illustrated in the below tables.

Adjustable Vector Length Class Operations Registers Instruction A (FIG.710, 715, zmm Templates that 7A; U = 0) 725, 730 registers (the do notinclude vector length is the vector length 64 byte) field 759B B (FIG.712 zmm 7B; U = 1) registers (the vector length is 64 byte) InstructionB (FIG. 717, 727 zmm, Templates that 7B; U = 1) ymm, or xmm do includethe registers (the vector length vector length is field 759B 64 byte, 32byte, or 16 byte) depending on the vector length field 759B

In other words, the vector length field 759B selects between a maximumlength and one or more other shorter lengths, where each such shorterlength is half the length of the preceding length; and instructionstemplates without the vector length field 759B operate on the maximumvector length. Further, in one embodiment, the class B instructiontemplates of the specific vector friendly instruction format 800 operateon packed or scalar single/double-precision floating point data andpacked or scalar integer data. Scalar operations are operationsperformed on the lowest order data element position in an zmm/ymm/xmmregister; the higher order data element positions are either left thesame as they were prior to the instruction or zeroed depending on theembodiment.

Write mask registers 915—in the embodiment illustrated, there are 8write mask registers (k0 through k7), each 64 bits in size. In analternate embodiment, the write mask registers 915 are 16 bits in size.As previously described, in one embodiment of the invention, the vectormask register k0 cannot be used as a write mask; when the encoding thatwould normally indicate k0 is used for a write mask, it selects ahardwired write mask of 0xFFFF, effectively disabling write masking forthat instruction.

General-purpose registers 925—in the embodiment illustrated, there aresixteen 64-bit general-purpose registers that are used along with theexisting x86 addressing modes to address memory operands. Theseregisters are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI,RSP, and R8 through R15.

Scalar floating point stack register file (x87 stack) 945, on which isaliased the MMX packed integer flat register file 950—in the embodimentillustrated, the x87 stack is an eight-element stack used to performscalar floating-point operations on 32/64/80-bit floating point datausing the x87 instruction set extension; while the MMX registers areused to perform operations on 64-bit packed integer data, as well as tohold operands for some operations performed between the MMX and XMMregisters.

Alternative embodiments of the invention may use wider or narrowerregisters. Additionally, alternative embodiments of the invention mayuse more, less, or different register files and registers.

Exemplary Core Architectures, Processors, and Computer Architectures

Processor cores may be implemented in different ways, for differentpurposes, and in different processors. For instance, implementations ofsuch cores may include: 1) a general purpose in-order core intended forgeneral-purpose computing; 2) a high performance general purposeout-of-order core intended for general-purpose computing; 3) a specialpurpose core intended primarily for graphics and/or scientific(throughput) computing. Implementations of different processors mayinclude: 1) a CPU including one or more general purpose in-order coresintended for general-purpose computing and/or one or more generalpurpose out-of-order cores intended for general-purpose computing; and2) a coprocessor including one or more special purpose cores intendedprimarily for graphics and/or scientific (throughput). Such differentprocessors lead to different computer system architectures, which mayinclude: 1) the coprocessor on a separate chip from the CPU; 2) thecoprocessor on a separate die in the same package as a CPU; 3) thecoprocessor on the same die as a CPU (in which case, such a coprocessoris sometimes referred to as special purpose logic, such as integratedgraphics and/or scientific (throughput) logic, or as special purposecores); and 4) a system on a chip that may include on the same die thedescribed CPU (sometimes referred to as the application core(s) orapplication processor(s)), the above described coprocessor, andadditional functionality. Exemplary core architectures are describednext, followed by descriptions of exemplary processors and computerarchitectures.

Exemplary Core Architectures

In-order and Out-of-order Core Block Diagram

FIG. 10A is a block diagram illustrating both an exemplary in-orderpipeline and an exemplary register renaming, out-of-orderissue/execution pipeline according to embodiments of the invention. FIG.10B is a block diagram illustrating both an exemplary embodiment of anin-order architecture core and an exemplary register renaming,out-of-order issue/execution architecture core to be included in aprocessor according to embodiments of the invention. The solid linedboxes in FIGS. 10A-B illustrate the in-order pipeline and in-order core,while the optional addition of the dashed lined boxes illustrates theregister renaming, out-of-order issue/execution pipeline and core. Giventhat the in-order aspect is a subset of the out-of-order aspect, theout-of-order aspect will be described.

In FIG. 10A, a processor pipeline 1000 includes a fetch stage 1002, alength decode stage 1004, a decode stage 1006, an allocation stage 1008,a renaming stage 1010, a scheduling (also known as a dispatch or issue)stage 1012, a register read/memory read stage 1014, an execute stage1016, a write back/memory write stage 1018, an exception handling stage1022, and a commit stage 1024.

FIG. 10B shows processor core 1090 including a front end unit 1030coupled to an execution engine unit 1050, and both are coupled to amemory unit 1070. The core 1090 may be a reduced instruction setcomputing (RISC) core, a complex instruction set computing (CISC) core,a very long instruction word (VLIW) core, or a hybrid or alternativecore type. As yet another option, the core 1090 may be a special-purposecore, such as, for example, a network or communication core, compressionengine, coprocessor core, general purpose computing graphics processingunit (GPGPU) core, graphics core, or the like.

The front end unit 1030 includes a branch prediction unit 1032 coupledto an instruction cache unit 1034, which is coupled to an instructiontranslation lookaside buffer (TLB) 1036, which is coupled to aninstruction fetch unit 1038, which is coupled to a decode unit 1040. Thedecode unit 1040 (or decoder) may decode instructions, and generate asan output one or more micro-operations, micro-code entry points,microinstructions, other instructions, or other control signals, whichare decoded from, or which otherwise reflect, or are derived from, theoriginal instructions. The decode unit 1040 may be implemented usingvarious different mechanisms. Examples of suitable mechanisms include,but are not limited to, look-up tables, hardware implementations,programmable logic arrays (PLAs), microcode read only memories (ROMs),etc. In one embodiment, the core 1090 includes a microcode ROM or othermedium that stores microcode for certain macroinstructions (e.g., indecode unit 1040 or otherwise within the front end unit 1030). Thedecode unit 1040 is coupled to a rename/allocator unit 1052 in theexecution engine unit 1050.

The execution engine unit 1050 includes the rename/allocator unit 1052coupled to a retirement unit 1054 and a set of one or more schedulerunit(s) 1056. The scheduler unit(s) 1056 represents any number ofdifferent schedulers, including reservations stations, centralinstruction window, etc. The scheduler unit(s) 1056 is coupled to thephysical register file(s) unit(s) 1058. Each of the physical registerfile(s) units 1058 represents one or more physical register files,different ones of which store one or more different data types, such asscalar integer, scalar floating point, packed integer, packed floatingpoint, vector integer, vector floating point, status (e.g., aninstruction pointer that is the address of the next instruction to beexecuted), etc. In one embodiment, the physical register file(s) unit1058 comprises a vector registers unit, a write mask registers unit, anda scalar registers unit. These register units may provide architecturalvector registers, vector mask registers, and general purpose registers.The physical register file(s) unit(s) 1058 is overlapped by theretirement unit 1054 to illustrate various ways in which registerrenaming and out-of-order execution may be implemented (e.g., using areorder buffer(s) and a retirement register file(s); using a futurefile(s), a history buffer(s), and a retirement register file(s); using aregister maps and a pool of registers; etc.). The retirement unit 1054and the physical register file(s) unit(s) 1058 are coupled to theexecution cluster(s) 1060. The execution cluster(s) 1060 includes a setof one or more execution units 1062 and a set of one or more memoryaccess units 1064. The execution units 1062 may perform variousoperations (e.g., shifts, addition, subtraction, multiplication) and onvarious types of data (e.g., scalar floating point, packed integer,packed floating point, vector integer, vector floating point). Whilesome embodiments may include a number of execution units dedicated tospecific functions or sets of functions, other embodiments may includeonly one execution unit or multiple execution units that all perform allfunctions. The scheduler unit(s) 1056, physical register file(s) unit(s)1058, and execution cluster(s) 1060 are shown as being possibly pluralbecause certain embodiments create separate pipelines for certain typesof data/operations (e.g., a scalar integer pipeline, a scalar floatingpoint/packed integer/packed floating point/vector integer/vectorfloating point pipeline, and/or a memory access pipeline that each havetheir own scheduler unit, physical register file(s) unit, and/orexecution cluster—and in the case of a separate memory access pipeline,certain embodiments are implemented in which only the execution clusterof this pipeline has the memory access unit(s) 1064). It should also beunderstood that where separate pipelines are used, one or more of thesepipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units 1064 is coupled to the memory unit 1070,which includes a data TLB unit 1072 coupled to a data cache unit 1074coupled to a level 2 (L2) cache unit 1076. In one exemplary embodiment,the memory access units 1064 may include a load unit, a store addressunit, and a store data unit, each of which is coupled to the data TLBunit 1072 in the memory unit 1070. The instruction cache unit 1034 isfurther coupled to a level 2 (L2) cache unit 1076 in the memory unit1070. The L2 cache unit 1076 is coupled to one or more other levels ofcache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-orderissue/execution core architecture may implement the pipeline 1000 asfollows: 1) the instruction fetch 1038 performs the fetch and lengthdecoding stages 1002 and 1004; 2) the decode unit 1040 performs thedecode stage 1006; 3) the rename/allocator unit 1052 performs theallocation stage 1008 and renaming stage 1010; 4) the scheduler unit(s)1056 performs the schedule stage 1012; 5) the physical register file(s)unit(s) 1058 and the memory unit 1070 perform the register read/memoryread stage 1014; the execution cluster 1060 perform the execute stage1016; 6) the memory unit 1070 and the physical register file(s) unit(s)1058 perform the write back/memory write stage 1018; 7) various unitsmay be involved in the exception handling stage 1022; and 8) theretirement unit 1054 and the physical register file(s) unit(s) 1058perform the commit stage 1024.

The core 1090 may support one or more instructions sets (e.g., the x86instruction set (with some extensions that have been added with newerversions); the MIPS instruction set of MIPS Technologies of Sunnyvale,Calif.; the ARM instruction set (with optional additional extensionssuch as NEON) of ARM Holdings of Sunnyvale, Calif.), including theinstruction(s) described herein. In one embodiment, the core 1090includes logic to support a packed data instruction set extension (e.g.,AVX1, AVX2, and/or some form of the generic vector friendly instructionformat (U=0 and/or U=1) previously described), thereby allowing theoperations used by many multimedia applications to be performed usingpacked data.

It should be understood that the core may support multithreading(executing two or more parallel sets of operations or threads), and maydo so in a variety of ways including time sliced multithreading,simultaneous multithreading (where a single physical core provides alogical core for each of the threads that physical core issimultaneously multithreading), or a combination thereof (e.g., timesliced fetching and decoding and simultaneous multithreading thereaftersuch as in the Intel® Hyperthreading technology).

While register renaming is described in the context of out-of-orderexecution, it should be understood that register renaming may be used inan in-order architecture. While the illustrated embodiment of theprocessor also includes separate instruction and data cache units1034/1074 and a shared L2 cache unit 1076, alternative embodiments mayhave a single internal cache for both instructions and data, such as,for example, a Level 1 (L1) internal cache, or multiple levels ofinternal cache. In some embodiments, the system may include acombination of an internal cache and an external cache that is externalto the core and/or the processor. Alternatively, all of the cache may beexternal to the core and/or the processor.

Specific Exemplary In-Order Core Architecture

FIGS. 11A-B illustrate a block diagram of a more specific exemplaryin-order core architecture, which core would be one of several logicblocks (including other cores of the same type and/or different types)in a chip. The logic blocks communicate through a high-bandwidthinterconnect network (e.g., a ring network) with some fixed functionlogic, memory I/O interfaces, and other necessary I/O logic, dependingon the application.

FIG. 11A is a block diagram of a single processor core, along with itsconnection to the on-die interconnect network 1102 and with its localsubset of the Level 2 (L2) cache 1104, according to embodiments of theinvention. In one embodiment, an instruction decoder 1100 supports thex86 instruction set with a packed data instruction set extension. An L1cache 1106 allows low-latency accesses to cache memory into the scalarand vector units. While in one embodiment (to simplify the design), ascalar unit 1108 and a vector unit 1110 use separate register sets(respectively, scalar registers 1112 and vector registers 1114) and datatransferred between them is written to memory and then read back in froma level 1 (L1) cache 1106, alternative embodiments of the invention mayuse a different approach (e.g., use a single register set or include acommunication path that allow data to be transferred between the tworegister files without being written and read back).

The local subset of the L2 cache 1104 is part of a global L2 cache thatis divided into separate local subsets, one per processor core. Eachprocessor core has a direct access path to its own local subset of theL2 cache 1104. Data read by a processor core is stored in its L2 cachesubset 1104 and can be accessed quickly, in parallel with otherprocessor cores accessing their own local L2 cache subsets. Data writtenby a processor core is stored in its own L2 cache subset 1104 and isflushed from other subsets, if necessary. The ring network ensurescoherency for shared data. The ring network is bi-directional to allowagents such as processor cores, L2 caches and other logic blocks tocommunicate with each other within the chip. Each ring data-path is1012-bits wide per direction.

FIG. 11B is an expanded view of part of the processor core in FIG. 11Aaccording to embodiments of the invention. FIG. 11B includes an L1 datacache 1106A part of the L1 cache 1104, as well as more detail regardingthe vector unit 1110 and the vector registers 1114. Specifically, thevector unit 1110 is a 16-wide vector processing unit (VPU) (see the16-wide ALU 1128), which executes one or more of integer,single-precision float, and double-precision float instructions. The VPUsupports swizzling the register inputs with swizzle unit 1120, numericconversion with numeric convert units 1122A-B, and replication withreplication unit 1124 on the memory input. Write mask registers 1126allow predicating resulting vector writes.

Processor with Integrated Memory Controller and Graphics

FIG. 12 is a block diagram of a processor 1200 that may have more thanone core, may have an integrated memory controller, and may haveintegrated graphics according to embodiments of the invention. The solidlined boxes in FIG. 12 illustrate a processor 1200 with a single core1202A, a system agent 1210, a set of one or more bus controller units1216, while the optional addition of the dashed lined boxes illustratesan alternative processor 1200 with multiple cores 1202A-N, a set of oneor more integrated memory controller unit(s) 1214 in the system agentunit 1210, and special purpose logic 1208.

Thus, different implementations of the processor 1200 may include: 1) aCPU with the special purpose logic 1208 being integrated graphics and/orscientific (throughput) logic (which may include one or more cores), andthe cores 1202A-N being one or more general purpose cores (e.g., generalpurpose in-order cores, general purpose out-of-order cores, acombination of the two); 2) a coprocessor with the cores 1202A-N being alarge number of special purpose cores intended primarily for graphicsand/or scientific (throughput); and 3) a coprocessor with the cores1202A-N being a large number of general purpose in-order cores. Thus,the processor 1200 may be a general-purpose processor, coprocessor orspecial-purpose processor, such as, for example, a network orcommunication processor, compression engine, graphics processor, GPGPU(general purpose graphics processing unit), a high-throughput manyintegrated core (MIC) coprocessor (including 30 or more cores), embeddedprocessor, or the like. The processor may be implemented on one or morechips. The processor 1200 may be a part of and/or may be implemented onone or more substrates using any of a number of process technologies,such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within thecores, a set or one or more shared cache units 1206, and external memory(not shown) coupled to the set of integrated memory controller units1214. The set of shared cache units 1206 may include one or moremid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), orother levels of cache, a last level cache (LLC), and/or combinationsthereof. While in one embodiment a ring based interconnect unit 1212interconnects the integrated graphics logic 1208, the set of sharedcache units 1206, and the system agent unit 1210/integrated memorycontroller unit(s) 1214, alternative embodiments may use any number ofwell-known techniques for interconnecting such units. In one embodiment,coherency is maintained between one or more cache units 1206 and cores1202-A-N.

In some embodiments, one or more of the cores 1202A-N are capable ofmulti-threading. The system agent 1210 includes those componentscoordinating and operating cores 1202A-N. The system agent unit 1210 mayinclude for example a power control unit (PCU) and a display unit. ThePCU may be or include logic and components needed for regulating thepower state of the cores 1202A-N and the integrated graphics logic 1208.The display unit is for driving one or more externally connecteddisplays.

The cores 1202A-N may be homogenous or heterogeneous in terms ofarchitecture instruction set; that is, two or more of the cores 1202A-Nmay be capable of execution the same instruction set, while others maybe capable of executing only a subset of that instruction set or adifferent instruction set.

Exemplary Computer Architectures

FIGS. 13-16 are block diagrams of exemplary computer architectures.Other system designs and configurations known in the arts for laptops,desktops, handheld PCs, personal digital assistants, engineeringworkstations, servers, network devices, network hubs, switches, embeddedprocessors, digital signal processors (DSPs), graphics devices, videogame devices, set-top boxes, micro controllers, cell phones, portablemedia players, hand held devices, and various other electronic devices,are also suitable. In general, a huge variety of systems or electronicdevices capable of incorporating a processor and/or other executionlogic as disclosed herein are generally suitable.

Referring now to FIG. 13, shown is a block diagram of a system 1300 inaccordance with one embodiment of the present invention. The system 1300may include one or more processors 1310, 1315, which are coupled to acontroller hub 1320. In one embodiment the controller hub 1320 includesa graphics memory controller hub (GMCH) 1390 and an Input/Output Hub(IOH) 1350 (which may be on separate chips); the GMCH 1390 includesmemory and graphics controllers to which are coupled memory 1340 and acoprocessor 1345; the IOH 1350 is couples input/output (I/O) devices1360 to the GMCH 1390. Alternatively, one or both of the memory andgraphics controllers are integrated within the processor (as describedherein), the memory 1340 and the coprocessor 1345 are coupled directlyto the processor 1310, and the controller hub 1320 in a single chip withthe IOH 1350.

The optional nature of additional processors 1315 is denoted in FIG. 13with broken lines. Each processor 1310, 1315 may include one or more ofthe processing cores described herein and may be some version of theprocessor 1200.

The memory 1340 may be, for example, dynamic random access memory(DRAM), phase change memory (PCM), or a combination of the two. For atleast one embodiment, the controller hub 1320 communicates with theprocessor(s) 1310, 1315 via a multi-drop bus, such as a frontside bus(FSB), point-to-point interface such as QuickPath Interconnect (QPI), orsimilar connection 1395.

In one embodiment, the coprocessor 1345 is a special-purpose processor,such as, for example, a high-throughput MIC processor, a network orcommunication processor, compression engine, graphics processor, GPGPU,embedded processor, or the like. In one embodiment, controller hub 1320may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources1310, 1315 in terms of a spectrum of metrics of merit includingarchitectural, microarchitectural, thermal, power consumptioncharacteristics, and the like.

In one embodiment, the processor 1310 executes instructions that controldata processing operations of a general type. Embedded within theinstructions may be coprocessor instructions. The processor 1310recognizes these coprocessor instructions as being of a type that shouldbe executed by the attached coprocessor 1345. Accordingly, the processor1310 issues these coprocessor instructions (or control signalsrepresenting coprocessor instructions) on a coprocessor bus or otherinterconnect, to coprocessor 1345. Coprocessor(s) 1345 accept andexecute the received coprocessor instructions.

Referring now to FIG. 14, shown is a block diagram of a first morespecific exemplary system 1400 in accordance with an embodiment of thepresent invention. As shown in FIG. 14, multiprocessor system 1400 is apoint-to-point interconnect system, and includes a first processor 1470and a second processor 1480 coupled via a point-to-point interconnect1450. Each of processors 1470 and 1480 may be some version of theprocessor 1200. In one embodiment of the invention, processors 1470 and1480 are respectively processors 1310 and 1315, while coprocessor 1438is coprocessor 1345. In another embodiment, processors 1470 and 1480 arerespectively processor 1310 coprocessor 1345.

Processors 1470 and 1480 are shown including integrated memorycontroller (IMC) units 1472 and 1482, respectively. Processor 1470 alsoincludes as part of its bus controller units point-to-point (P-P)interfaces 1476 and 1478; similarly, second processor 1480 includes P-Pinterfaces 1486 and 1488. Processors 1470, 1480 may exchange informationvia a point-to-point (P-P) interface 1450 using P-P interface circuits1478, 1488. As shown in FIG. 14, IMCs 1472 and 1482 couple theprocessors to respective memories, namely a memory 1432 and a memory1434, which may be portions of main memory locally attached to therespective processors.

Processors 1470, 1480 may each exchange information with a chipset 1490via individual P-P interfaces 1452, 1454 using point to point interfacecircuits 1476, 1494, 1486, 1498. Chipset 1490 may optionally exchangeinformation with the coprocessor 1438 via a high-performance interface1439. In one embodiment, the coprocessor 1438 is a special-purposeprocessor, such as, for example, a high-throughput MIC processor, anetwork or communication processor, compression engine, graphicsprocessor, GPGPU, embedded processor, or the like.

A shared cache (not shown) may be included in either processor oroutside of both processors, yet connected with the processors via P-Pinterconnect, such that either or both processors' local cacheinformation may be stored in the shared cache if a processor is placedinto a low power mode.

Chipset 1490 may be coupled to a first bus 1416 via an interface 1496.In one embodiment, first bus 1416 may be a Peripheral ComponentInterconnect (PCI) bus, or a bus such as a PCI Express bus or anotherthird generation I/O interconnect bus, although the scope of the presentinvention is not so limited.

As shown in FIG. 14, various I/O devices 1414 may be coupled to firstbus 1416, along with a bus bridge 1418 which couples first bus 1416 to asecond bus 1420. In one embodiment, one or more additional processor(s)1415, such as coprocessors, high-throughput MIC processors, GPGPU's,accelerators (such as, e.g., graphics accelerators or digital signalprocessing (DSP) units), field programmable gate arrays, or any otherprocessor, are coupled to first bus 1416. In one embodiment, second bus1420 may be a low pin count (LPC) bus. Various devices may be coupled toa second bus 1420 including, for example, a keyboard and/or mouse 1422,communication devices 1427 and a storage unit 1428 such as a disk driveor other mass storage device which may include instructions/code anddata 1430, in one embodiment. Further, an audio I/O 1424 may be coupledto the second bus 1420. Note that other architectures are possible. Forexample, instead of the point-to-point architecture of FIG. 14, a systemmay implement a multi-drop bus or other such architecture.

Referring now to FIG. 15, shown is a block diagram of a second morespecific exemplary system 1500 in accordance with an embodiment of thepresent invention Like elements in FIGS. 14 and 15 bear like referencenumerals, and certain aspects of FIG. 14 have been omitted from FIG. 15in order to avoid obscuring other aspects of FIG. 15.

FIG. 15 illustrates that the processors 1470, 1480 may includeintegrated memory and I/O control logic (“CL”) 1472 and 1482,respectively. Thus, the CL 1472, 1482 include integrated memorycontroller units and include I/O control logic. FIG. 15 illustrates thatnot only are the memories 1432, 1434 coupled to the CL 1472, 1482, butalso that I/O devices 1514 are also coupled to the control logic 1472,1482. Legacy I/O devices 1515 are coupled to the chipset 1490.

Referring now to FIG. 16, shown is a block diagram of a SoC 1600 inaccordance with an embodiment of the present invention. Similar elementsin FIG. 12 bear like reference numerals. Also, dashed lined boxes areoptional features on more advanced SoCs. In FIG. 16, an interconnectunit(s) 1602 is coupled to: an application processor 1610 which includesa set of one or more cores 202A-N and shared cache unit(s) 1206; asystem agent unit 1210; a bus controller unit(s) 1216; an integratedmemory controller unit(s) 1214; a set or one or more coprocessors 1620which may include integrated graphics logic, an image processor, anaudio processor, and a video processor; an static random access memory(SRAM) unit 1630; a direct memory access (DMA) unit 1632; and a displayunit 1640 for coupling to one or more external displays. In oneembodiment, the coprocessor(s) 1620 include a special-purpose processor,such as, for example, a network or communication processor, compressionengine, GPGPU, a high-throughput MIC processor, embedded processor, orthe like.

Embodiments of the mechanisms disclosed herein may be implemented inhardware, software, firmware, or a combination of such implementationapproaches. Embodiments of the invention may be implemented as computerprograms or program code executing on programmable systems comprising atleast one processor, a storage system (including volatile andnon-volatile memory and/or storage elements), at least one input device,and at least one output device.

Program code, such as code 1430 illustrated in FIG. 14, may be appliedto input instructions to perform the functions described herein andgenerate output information. The output information may be applied toone or more output devices, in known fashion. For purposes of thisapplication, a processing system includes any system that has aprocessor, such as, for example; a digital signal processor (DSP), amicrocontroller, an application specific integrated circuit (ASIC), or amicroprocessor.

The program code may be implemented in a high level procedural or objectoriented programming language to communicate with a processing system.The program code may also be implemented in assembly or machinelanguage, if desired. In fact, the mechanisms described herein are notlimited in scope to any particular programming language. In any case,the language may be a compiled or interpreted language.

One or more aspects of at least one embodiment may be implemented byrepresentative instructions stored on a machine-readable medium whichrepresents various logic within the processor, which when read by amachine causes the machine to fabricate logic to perform the techniquesdescribed herein. Such representations, known as “IP cores” may bestored on a tangible, machine readable medium and supplied to variouscustomers or manufacturing facilities to load into the fabricationmachines that actually make the logic or processor.

Such machine-readable storage media may include, without limitation,non-transitory, tangible arrangements of articles manufactured or formedby a machine or device, including storage media such as hard disks, anyother type of disk including floppy disks, optical disks, compact diskread-only memories (CD-ROMs), compact disk rewritable's (CD-RWs), andmagneto-optical disks, semiconductor devices such as read-only memories(ROMs), random access memories (RAMs) such as dynamic random accessmemories (DRAMs), static random access memories (SRAMs), erasableprogrammable read-only memories (EPROMs), flash memories, electricallyerasable programmable read-only memories (EEPROMs), phase change memory(PCM), magnetic or optical cards, or any other type of media suitablefor storing electronic instructions.

Accordingly, embodiments of the invention also include non-transitory,tangible machine-readable media containing instructions or containingdesign data, such as Hardware Description Language (HDL), which definesstructures, circuits, apparatuses, processors and/or system featuresdescribed herein. Such embodiments may also be referred to as programproducts.

Emulation (Including Binary Translation, Code Morphing, etc.)

In some cases, an instruction converter may be used to convert aninstruction from a source instruction set to a target instruction set.For example, the instruction converter may translate (e.g., using staticbinary translation, dynamic binary translation including dynamiccompilation), morph, emulate, or otherwise convert an instruction to oneor more other instructions to be processed by the core. The instructionconverter may be implemented in software, hardware, firmware, or acombination thereof. The instruction converter may be on processor, offprocessor, or part on and part off processor.

FIG. 17 is a block diagram contrasting the use of a software instructionconverter to convert binary instructions in a source instruction set tobinary instructions in a target instruction set according to embodimentsof the invention. In the illustrated embodiment, the instructionconverter is a software instruction converter, although alternativelythe instruction converter may be implemented in software, firmware,hardware, or various combinations thereof. FIG. 17 shows a program in ahigh level language 1702 may be compiled using an x86 compiler 1704 togenerate x86 binary code 1706 that may be natively executed by aprocessor with at least one x86 instruction set core 1716. The processorwith at least one x86 instruction set core 1716 represents any processorthat can perform substantially the same functions as an Intel processorwith at least one x86 instruction set core by compatibly executing orotherwise processing (1) a substantial portion of the instruction set ofthe Intel x86 instruction set core or (2) object code versions ofapplications or other software targeted to run on an Intel processorwith at least one x86 instruction set core, in order to achievesubstantially the same result as an Intel processor with at least onex86 instruction set core. The x86 compiler 1704 represents a compilerthat is operable to generate x86 binary code 1706 (e.g., object code)that can, with or without additional linkage processing, be executed onthe processor with at least one x86 instruction set core 1716.Similarly, FIG. 17 shows the program in the high level language 1702 maybe compiled using an alternative instruction set compiler 1708 togenerate alternative instruction set binary code 1710 that may benatively executed by a processor without at least one x86 instructionset core 1714 (e.g., a processor with cores that execute the MIPSinstruction set of MIPS Technologies of Sunnyvale, Calif. and/or thatexecute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.).The instruction converter 1712 is used to convert the x86 binary code1706 into code that may be natively executed by the processor without anx86 instruction set core 1714. This converted code is not likely to bethe same as the alternative instruction set binary code 1710 because aninstruction converter capable of this is difficult to make; however, theconverted code will accomplish the general operation and be made up ofinstructions from the alternative instruction set. Thus, the instructionconverter 1712 represents software, firmware, hardware, or a combinationthereof that, through emulation, simulation or any other process, allowsa processor or other electronic device that does not have an x86instruction set processor or core to execute the x86 binary code 1706.

What is claimed is:
 1. An apparatus comprising: a decoder to decode asingle multiply add instruction into a decoded single multiply addinstruction; and an instruction execution pipeline having a functionalunit to execute the decoded single multiply add instruction to multiplyrespective K bit sections of a first X bit input operand and a second Xbit input operand to generate a product, wherein X is greater than K,and accumulate the product with a third input operand in an accumulatorto generate a resultant, wherein the sections are first sections when afield of the single multiply add instruction is a first value and thesections are non-overlapping second sections when the field is a secondvalue.
 2. The apparatus of claim 1, wherein X and K are specified in aninstruction format of the single multiply add instruction.
 3. Theapparatus of claim 1, wherein the functional unit comprises a path tostore the resultant into storage for the third input operand.
 4. Theapparatus of claim 3, wherein the storage is X bits and the third inputoperand is K bits of the storage.
 5. The apparatus of claim 1, where Kis 52 and X is
 64. 6. The apparatus of claim 1, wherein X is a nominalbit width of data processed by the instruction execution pipeline. 7.The apparatus of claim 1, wherein the first sections are upper halvesand the non-overlapping second sections are lower halves.
 8. Theapparatus of claim 1, wherein the functional unit executes the decodedsingle multiply add instruction to multiply the respective K bitsections to generate the product without implementing any carry flag. 9.A method comprising: decoding a single multiply add instruction into adecoded single multiply add instruction with a decoder of a processor;and executing the decoded single multiply add instruction with aninstruction execution pipeline of the processor having a functional unitto multiply respective K bit sections of a first X bit input operand anda second X bit input operand to generate a product, wherein X is greaterthan K, and accumulate the product with a third input operand in anaccumulator to generate a resultant, wherein the sections are firstsections when a field of the single multiply add instruction is a firstvalue and the sections are non-overlapping second sections when thefield is a second value.
 10. The method of claim 9, wherein X and K arespecified in an instruction format of the single multiply addinstruction.
 11. The method of claim 9, wherein executing the decodedsingle multiply add instruction causes the resultant to be stored intostorage for the third input operand.
 12. The method of claim 11, whereinthe storage is X bits and the third input operand is K bits of thestorage.
 13. The method of claim 9, where K is 52 and X is
 64. 14. Themethod of claim 9, wherein X is a nominal bit width of data processed bythe instruction execution pipeline.
 15. The method of claim 9, whereinthe first sections are upper halves and the non-overlapping secondsections are lower halves.
 16. The method of claim 9, wherein theexecuting is to multiply the respective K bit sections to generate theproduct without implementing any carry flag.
 17. A non-transitorymachine readable medium that stores code that when executed by a machinecauses the machine to perform a method comprising: decoding a singlemultiply add instruction into a decoded single multiply add instructionwith a decoder of a processor; and executing the decoded single multiplyadd instruction with an instruction execution pipeline of the processorhaving a functional unit to multiply respective K bit sections of afirst X bit input operand and a second X bit input operand to generate aproduct, wherein X is greater than K, and accumulate the product with athird input operand in an accumulator to generate a resultant, whereinthe sections are first sections when a field of the single multiply addinstruction is a first value and the sections are non-overlapping secondsections when the field is a second value.
 18. The non-transitorymachine readable medium of claim 17, wherein X and K are specified in aninstruction format of the single multiply add instruction.
 19. Thenon-transitory machine readable medium of claim 17, wherein executingthe decoded single multiply add instruction causes the resultant to bestored into storage for the third input operand.
 20. The non-transitorymachine readable medium of claim 19, wherein the storage is X bits andthe third input operand is K bits of the storage.
 21. The non-transitorymachine readable medium of claim 17, where K is 52 and X is
 64. 22. Thenon-transitory machine readable medium of claim 17, wherein X is anominal bit width of data processed by the instruction executionpipeline.
 23. The non-transitory machine readable medium of claim 17,wherein the first sections are upper halves and the non-overlappingsecond sections are lower halves.
 24. The non-transitory machinereadable medium of claim 17, wherein the executing is to multiply therespective K bit sections to generate the product without implementingany carry flag.